ProDigital Pty Limited



With emphasis on "DESIGN FOR TEST", being a major criteria for high quality production, JTAG Technologies along with Aster Technologies provide a complete suite of tools to address every possible challenge to achieve maximum board test coverage.

JTAG Technologies - from prototype to manufacturing and also able to provide full "turn-Key" run-time solutions including test fixture.

High pin count, complex SMD's available in packages such as uBGA for example, present accessability challenges for the traditonal ATE test fixture approach.
Even if these pins were physically accessable, the number of pins per square centimeter would impose unreasonable vaccum pressures on a fixture.

In 1993, JTAG Technologies, the creators of IEEE 1149.1, introduced Boundary Scan technology to the electronic industry. Today, several devices, including microprocessors, offered by semiconductor vendors, are being manufactured with boundary scan cells. This means, for most part, only a 5 pin header is required (Test Access Port) to interface to the PCB and competely test all devices on a JTAG NET LIST from infrastructure testing to interconnectivity, cluster testing, connectivity to memory devices and also in-circuit program Flash and CPLD's.

Testing with Boundary scan still maintains the original principle that if a pin can be driven and the result sensed from another pin, then it is testable.
Non-boundary scan components within that netlist can have their interconnectivity tested also.

JTAG Live Studio ....... is a suite of tools for design engineers.
It can also be used in low volume production but high skilled operators would be required.
These tools are the equivalent of a boundary scan version of an Ohmmeter, Oscilloscope and much more.
Once given a netlist and BSDL files, it can immediately perform an Infrastructure test to determine the integrity of the Boundary Scan chain.
Once this passes, all other tools can be used. A fault report is generated to highlight any existing failures

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Buzz Is a continuity tester to measure connectivity between any two nominated points on a net.
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BuzzPlus is the same but you can Buzz multiple nets at the same time or see what other connections a particular net is connected to.
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AutoBuzz can do a learn from a good board and then compare to a board under test and highlights any differences.
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CoreCommander Is the newest for ARM or Cortex devices and allows you to do tests at full speed and access features of the device.
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Clip - Like a logic ananlyzer, nets can be driven and read back for a result.
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Script Is based on a Free commonly used language Python, whereby you can write any application manually and generate a specific test.

JTAG ProVison - Automated test generation for Interconnect-FLASH-CPLD are created from given netlist and BSDL files.
This video link above is a tutorial which demonstrates how ProVision generates applications automatically for you given a netlist and proper BSDL files for the devices used in the design.
Send email for your pdf copy of "Why Does Boundary Make Sense" booklet.
Tools for the Design Engneers
Automatic Generation of test applications for production test.